17 Pages, 540 KB, Original
CPLD, ATV750B Family, EECMOS Process, 750 Gates, 10 Macro Cells, 20 Reg., 10 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
25 Pages, 188 KB, Original
CPLD ATV750 Family 10 Macro Cells 52MHz 0.65um, CMOS Technology 5V 24-Pin CDIP