d in DoubleCAD XT, (www.DoubleCAD.com) 66.03 mm 3.00 mm 2.54 mm 114 pin PGA to 132 pin W9874M 2.54 mm 6.24 mm 1.60 mm 33.02 mm Part Number W9621SDF request datasheet Product Group Solder Down Interface Modules - Device Specific Clearance Item False Device MC68020 Top Package 114 pin PGA Top Pitch 0.1" Bottom Package 132 pin W9874M Bottom Pitch 0.050" Note 1 W9874M sold seperately. 1.27 mm TITLE SIZE A4 CAGE CODE REV 1 DRAWN BY JW W9621SDF SCALE NTS SHEET

e from the Ministry of International Trade and Industry or other approval from another government agency. In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall be called 8085 and Motorola's MC6809 and MC6802 or their equivalents shall be called 6809 and 6802, respectively. (R) stands for registered trade mark. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. (c) Seiko Epson Corporation 2003 All rights reserved. Configuration of product number Devices S1 D 13706 F 00A0 00 Packing specification Specification Package (B: CSP, F: QFP) Corresponding model number Model name (D: driver, digital products) Product classification (S1: semiconductor) Evaluation Board S5U 13705 P00C0 00 Packing specification Specification Corresponding model number (13705: for S1D13705) Product classification (S5U: development tool for semiconductor) CONTENTS Table of Contents 1 Overview ....................

Freescale Semiconductor, Inc. SECTION 5 CENTRAL PROCESSING UNIT Freescale Semiconductor, Inc... The CPU32, the instruction processing module of the M68300 family, is based on the industry-standard MC68000 processor. It has many features of the MC68010 and MC68020, as well as unique features suited for high-performance controller applications. This section is an overview of the CPU32. For detailed information concerning CPU operation, refer to the CPU32 Reference Manual (CPU32RM/AD). 5.1 General Ease of programming is an important consideration in using a microcontroller. The CPU32 instruction format reflects a philosophy emphasizing register-memory interaction. There are eight multifunction data registers and seven general-purpose addressing registers. All data resources are available to all operations requiring those resources. The data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long-word) operand lengths for all operations. Word and long-word operations support address m

est Module Control Register $YFFA38 DREG --Test Module Distributed Register $YFFA3A MC68332 MC68332TS/D For More Information On This Product, Go to: www.freescale.com MOTOROLA 43 Freescale Semiconductor, Inc. 4 Central Processor Unit Based on the powerful MC68020, the CPU32 processing module provides enhanced system performance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview Freescale Semiconductor, Inc... The CPU32 is fully object code compatible with the M68000 Family, which excels at processing calculation-intensive algorithms and supporting high-level languages. The CPU32 supports all of the MC68010 and most of the MC68020 enhancements, such as virtual memory support, loop mode operation, instruction pipeline, and 32-bit mathematical operations. Powerful addressing modes provide compatibility with existing software programs and increase the efficiency of high-level language compilers. Special instructions, such as table lookup and interpolat

ge has a 25-mil pitch. * System Bus--The system bus signals now look like those of the MC68030 as opposed to those of the M68000. It is still possible to interface M68000 peripherals to the QUICC, utilizing the same techniques used to interface them to an MC68020 or MC68030. * System Bus in Slave Mode--A number of QUICC pins take on new functionality in slave mode to support an external MC68EC040. On the MC68302, the pin names generally remained the same in slave mode. * Peripheral Timing--The external timings of the peripherals (SCCs, timers, etc.) are very similar (if not identical) to corresponding peripherals on the MC68302. * Pin Assignments--The assignment of peripheral functions to I/O pins is different in several ways. First, the QUICC contains more general-purpose parallel I/O pins than the MC68302. However, the QUICC offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the MC68302. 1.3.3 Software Compatibility Issues Th

8336/376 Signal Characteristics .................................................................... 3-9 MC68336/376 Signal Functions........................................................................... 3-11 4-1 4-2 4-3 4-4 4-5 4-6 4-7 Unimplemented MC68020 Instructions................................................................ 4-10 Instruction Set Summary ..................................................................................... 4-11 Exception Vector Assignments ............................................................................ 4-17 BDM Source Summary ........................................................................................ 4-21 Polling the BDM Entry Source ............................................................................. 4-22 Background Mode Command Summary.............................................................. 4-23 CPU Generated Message Encoding.................................................................... 4-26 5-1 Show Cy

302 AN2016/D DRAM Control with the MC68302 MC68302 Getting Started with Interrupts on the MC68302 MC68302 Design Concept - Expanding Interrupts on AN2019/D the MC68302 MC68302 Adapting a WAN Controller to a LAN AN2020/D Environment MC68302 Interfacing the MC68020 to a Slave AN2021/D MC68302 MC68302 EKB Applications - Power Measurements AN2023/D on the MC68302 AN2024/D MC68302 Software Performance AN2026/D MC68302 Evaluating EDX on the ADS302 AN2018/D MC68302 Using the 302 Communications Peripheral for PowerPC Microprocessors MC68302 Design Advisory #1 - MC68SC302 Passive AN2028/D ISDN Protocol Engine MC68302, MC68360, and MPC860 Characteristics AN2049/D and Design Notes for Crystal Feedback Oscillators AN2027/D Format Size K Rev # Date Last Modified Order Availability pdf 62 0 6/17/1991 pdf 266 0 3/21/1991 pdf 30 0 3/14/1990 pdf 13 0 7/09/1990 pdf 515 0 1/01/1999 pdf 141 0 2/02/1993 pdf 45 1 7/26/1995 pdf 42 0 6/18/1990 pdf 167 0 2/27/1991 pdf 325 0 1/01/1994 pdf 5 0 3/31/1997 pdf 29 0 1/01/1998

O-CHANNEL DMA CONTROLLER TIMER TIMER IEEE TEST Figure 1-1. Block Diagram MOTOROLA MC68340 USER'S MANUAL 1-1 The primary features of the MC68340, illustrated in Figure 1-1, are as follows: * High Functional Integration on a Single Piece of Silicon * CPU32--MC68020-Derived 32-Bit Central Processor Unit -- Upward Object-Code Compatible with MC68000 and MC68010 -- Additional MC68020 Instructions and Addressing Modes -- Unique Embedded Control Instructions -- Fast Two-Clock Register Instructions--10,045 Dhrystones * Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers -- Single- or Dual-Address Transfers -- 32-Bit Addresses and Counters -- 8-, 16-, and 32-Bit Data Transfers -- 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory) * Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART) -- Baud Rate Generators -- Modem Control -- MC68681/MC2681 Compatible -- 9.8 Mbits/Sec Maximum Transfer Rate * Two Independent Counter/Timers -- 16-Bit Co

e disable CPU mode. This situation is as follows: For a slave-mode MC68302, when it is triggered by IRQ1, IRQ6, or IRQ7 to generate an interrupt, its interrupt controller will output the interrupt request on pins IOUT2-IOUT0 to another processor (MC68302, MC68020, etc.) For cases when the slave MC68302 does not generate a level 4 vector (i.e., the VGE bit is cleared), one must set the ET1, ET6, and ET7 bits to level-triggered and then negate the IRQ1, IRQ6, and IRQ7 lines externally in the interrupt handler code. If the ET1, ET6, and ET7 bits are set to edge-triggered and the VGE bit is clear, the IOUT2-IOUT0 pins will never be cleared. 1 = Edge-triggered. An interrupt is made pending when IRQ7 changes from one to zero (falling edge). ET6--IRQ6 Edge-/Level-Triggered This bit is valid only in the dedicated mode. 0 = Level-triggered. An interrupt is made pending when IRQ6 is low. NOTE While in disable CPU mode during the host processor interrupt acknowledge cycle for IRQ6, if IRQ6 is not continuous

are latched in accordingly. * compatible with Motorola and Intel processors. Figure 17 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the M6809, the chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe (DS). When DS is low, Motorola processor operation is selected. Figure 18 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode output. Again, the MT88s9C examines the state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370CX5X is qualified to have a M

V2nH + V2IMD THD (%) = 100 V2L + V2H Equation 2. THD (%) For a Dual Tone 4-78 Figure 16 shows the timing diagram for Motorola microprocessors with separate address and data buses. Members of this microprocessor family include 2 MHz versions of the MC6800, MC6802 and MC6809. For the MC6809, the chip select (CS) input signal is formed by NANDing the (E+Q) clocks and address decode output. For the MC6800 and MC6802, CS is formed by NANDing VMA and address decode output. On the falling edge of CS, the internal logic senses the state of data strobe MT88L85 Advance Information (DS). When DS is low, Motorola processor operation is selected. Figure 17 shows the timing diagram for the Motorola MC68HC11 (1 MHz) microcontroller. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode output. Again, the MT88L85 examines the state of DS on the falling edge of CS to determine if the micro has a Motorola bus (when DS is low). Additionally, the Texas Instruments TMS370

plete line of semiconductor products, call the Hotline. Design-Net FAX Service: (602) 244-6609 To obtain data sheets on Motorola semiconductors, call the automated Design-Net FAX Service. Motorola M68000 Family Upward Compatible 16-/32-Bit Microprocessors MC68020, 32-Bit HCMOS Microprocessor The 020 has a full 32-bit internal and 32-bit external, regular, symmetrical architecture. It offers all the functionality of the M68000 Family MPUs and maintains software user-code compatibility. The unique on-chip instruction cache helps provide burst-mode operation to 12.5 MIPS. The 020 is the proven leader in high performance systems in office Mfr.Os Type automation, engineering workstations, fault tolerant computers, parallel processors, telephone switching systems, and intelligent controllers. Operating Frequency (MHz) MIPS MFLOPS 114 Lead PGA (Gold Lead) Address Range (Bytes) Data Bus (Bit) Instruction Cache (Bytes) Data Cache (Bytes) Burst Mode General Purpose Registers Address Modes On-Chip MMU Float

roprocessor, which may operate in one of several modes compatible with most of the popular embedded microprocessor families. Four bus interface modes are supported: * Hitachi SH-3. * Motorola MC68000 (using Upper Data Strobe/Lower Data Strobe). * Motorola MC68020/MC68030/MC683xx (using Data Strobe/DSACKx). * Generic Bus (Chip Select, plus individual Read Enable/Write Enable for each byte). Mode selections are made during reset by sampling the state of the memory data lines. Table 5-6 in the SED1354 Hardware Functional Specification, document number X19-A-A-002-xx, and Table 5-5 in the SED1355 Hardware Functional Specification, X23A-A-001-xx, details the values needed the memory data lines, to select the desired mode. After releasing reset, the bus interface signals assume their selected configuration. Table 57 in the SED1354, or Table 5-6 in the SED1356 Hardware Functional Specification shows the function of each bus interface signal for each of the interface modes. Two other mode selections are

le Shift Count $YFFA34 TSTRC -- Test Module Repetition Count $YFFA36 CREG -- Test Module Control Register $YFFA38 DREG -- Test Module Distributed Register $YFFA3A MC68CK338 MC68CK338TS/D MOTOROLA 47 4 Low-Power Central Processor Unit Based on the powerful MC68020, the CPU32L processing module provides enhanced system performance and also uses the extensive software base for the Motorola M68000 family. 4.1 Overview The CPU32L is fully object-code compatible with the M68000 family, which excels at processing calculation-intensive algorithms and supporting high-level languages. The CPU32L supports all of the MC68010 and most of the MC68020 enhancements, such as virtual memory support, loop mode operation, instruction pipeline, and 32-bit mathematical operations. Powerful addressing modes provide compatibility with existing software programs and increase the efficiency of high-level language compilers. Special instructions, such as table lookup and interpolate and low-power stop, support

itle Misaligned Operands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of Dynamic Bus Sizing and Operand Misalignment . . . . . . Address, Size, and Data Bus Relationships . . . . . . . . . . . . . . . . . . MC68030 versus MC68020 Dynamic Bus Sizing . . . . . . . . . . . . . . Cache Filling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cache Interactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation with DSACKx . . . . . . . . . . . . . . . . . . . . . . Synchronous Operation with STERM . . . . . . . . . . . . . . . . . . . . . . . Data Transfer Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . .