T CMOS. See Table 5 for more information on possible combinations of interconnections. 14 Ordering Information (continued) PART SYSTEM POWERSUPPLY VOLTAGE (V) 5 Figure 12a. Transmitter Output Voltage vs. Load Current per Transmitter TEMP RANGE PIN-PACKAGE MAX3243ECWI+ 0C to +70C MAX3243ECAI+ 0C to +70C 28 Wide SO 28 SSOP MAX3243ECUI+ 0C to +70C 28 TSSOP MAX3243EEWI+ -40C to +85C 28 Wide SO MAX3243EEAI+ -40C to +85C 28 SSOP MAX3243EEUI+ -40C to +85C 28 TSSOP MAX3243ECTJ+ 0C to +70C 32 TQFN-EP* MAX3243EETJ+ -40C to +85C 32 TQFN-EP* *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. ___________________Chip Information PROCESS: BiCMOS Maxim Integrated MAX3221E/MAX3223E/MAX3243E 15kV ESD-Protected, 1A, 3.0V to 5.5V, 250kbps, RS-232 Transceivers with AutoShutdown +3.3V 26 0.1F 28 C1 0.1F 24 1 C2 0.1F 2 LOGIC INPUTS VCC 27 C1+ V+ C3 0.1F C1C2+ COMPUTER SERIAL PORT 3 MAX3243E V- C4 0.1F C2- 14 T1IN T1OUT 9 +V 13 T2IN T2OUT 10 +V 12 T3IN T3OUT 11 -V 20 R2OUTB 19 R1OUT GND R1IN 4 R2IN 5 Tx 5k 1

-free; # = RoHS/lead-exempt. More: See full data sheet or Part Naming Conventions. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Part Number MAX3243ECWI Free Sample Sample MAX3243ECWI-T MAX3243ECWI+ Sample MAX3243ECWI+T MAX3243EEWI+ MAX3243EEWI+T Buy Temp Package: TYPE PINS SIZE Direct DRAWING CODE/VAR * Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28-6* 0C to +70C RoHS/Lead-Free: No Materials Analysis Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28-6* 0C to +70C RoHS/Lead-Free: No Materials Analysis Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* 0C to +70C RoHS/Lead-Free: Yes SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* 0C to +70C Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* -40C to +85C RoHS/Lead-Free: Yes Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) -40C to +85C RoHS/Lead-Free: Yes Buy Sample RoHS/Le

-free; # = RoHS/lead-exempt. More: See full data sheet or Part Naming Conventions. * Some packages have variations, listed on the drawing. "PkgCode/Variation" tells which variation the product uses. Part Number MAX3243ECWI Free Sample Sample MAX3243ECWI-T MAX3243ECWI+ Sample MAX3243ECWI+T MAX3243EEWI+ MAX3243EEWI+T Buy Temp Package: TYPE PINS SIZE Direct DRAWING CODE/VAR * Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28-6* 0C to +70C RoHS/Lead-Free: No Materials Analysis Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28-6* 0C to +70C RoHS/Lead-Free: No Materials Analysis Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* 0C to +70C RoHS/Lead-Free: Yes SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* 0C to +70C Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) Use pkgcode/variation: W28+6* -40C to +85C RoHS/Lead-Free: Yes Buy SOIC;28 pin;.300" Dwg: 21-0042B (PDF) -40C to +85C RoHS/Lead-Free: Yes Buy Sample RoHS/Le

I MAX3243CUI+ MAX3243CUI+T MAX3243CUI-T MAX3243CWI MAX3243CWI+ MAX3243CWI+T MAX3243CWI-T MAX3243EAI MAX3243EAI+ MAX3243EAI+T MAX3243EAI-T MAX3243ECAI MAX3243ECAI+ MAX3243ECAI+T MAX3243ECAI-T MAX3243ECUI MAX3243ECUI+ MAX3243ECUI+T MAX3243ECUI-T MAX3243ECWI MAX3243ECWI+ MAX3243ECWI+T MAX3243ECWI-T MAX3243EEAI MAX3243EEAI+ MAX3243EEAI+T MAX3243EEAI-T MAX3243EEUI MAX3243EEUI+ MAX3243EEUI+T MAX3243EEUI-T MAX3243EEWI MAX3243EEWI+ MAX3243EEWI+T MAX3243EEWI-T MAX3243EUI MAX3243EUI+ MAX3243EUI+T MAX3243EUI-T MAX3243EWI MAX3243EWI+ MAX3243EWI+T MAX3243EWI-T MAX3243ICAI MAX3243ICAI+ MAX3243ICAI+T MAX3243ICAI-T MAX3243ICUI MAX3243ICUI+ MAX3243ICUI+T Competition Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxim Maxi

T CMOS. See Table 5 for more information on possible combinations of interconnections. 14 Ordering Information (continued) PART SYSTEM POWERSUPPLY VOLTAGE (V) 5 Figure 12a. Transmitter Output Voltage vs. Load Current per Transmitter TEMP RANGE PIN-PACKAGE MAX3243ECWI+ 0C to +70C 28 Wide SO MAX3243ECAI+ 0C to +70C 28 SSOP MAX3243ECUI+ 0C to +70C 28 TSSOP MAX3243EEWI+ -40C to +85C 28 Wide SO MAX3243EEAI+ -40C to +85C 28 SSOP MAX3243EEUI+ -40C to +85C 28 TSSOP MAX3243ECTJ+ 0C to +70C 32 TQFN-EP* MAX3243EETJ+ -40C to +85C 32 TQFN-EP* *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. ___________________Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 15kV ESD-Protected, 1A, 3.0V to 5.5V, 250kbps, RS-232 Transceivers with AutoShutdown MAX3221E/MAX3223E/MAX3243E +3.3V 26 0.1F 28 C1 0.1F 24 1 C2 0.1F 2 LOGIC INPUTS VCC 27 C1+ V+ C3 0.1F C1C2+ COMPUTER SERIAL PORT 3 MAX3243E V- C4 0.1F C2- 14 T1IN T1OUT 9 +V 13 T2IN T2OUT

T CMOS. See Table 5 for more information on possible combinations of interconnections. 14 Ordering Information (continued) PART SYSTEM POWERSUPPLY VOLTAGE (V) 5 Figure 12a. Transmitter Output Voltage vs. Load Current per Transmitter TEMP RANGE PIN-PACKAGE MAX3243ECWI+ 0C to +70C 28 Wide SO MAX3243ECAI+ 0C to +70C 28 SSOP MAX3243ECUI+ 0C to +70C 28 TSSOP MAX3243EEWI+ -40C to +85C 28 Wide SO MAX3243EEAI+ -40C to +85C 28 SSOP MAX3243EEUI+ -40C to +85C 28 TSSOP MAX3243ECTJ+ 0C to +70C 32 TQFN-EP* MAX3243EETJ+ -40C to +85C 32 TQFN-EP* *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. ___________________Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 15kV ESD-Protected, 1A, 3.0V to 5.5V, 250kbps, RS-232 Transceivers with AutoShutdown MAX3221E/MAX3223E/MAX3243E +3.3V 26 0.1F 28 C1 0.1F 24 1 C2 0.1F 2 LOGIC INPUTS VCC 27 C1+ V+ C3 0.1F C1C2+ COMPUTER SERIAL PORT 3 MAX3243E V- C4 0.1F C2- 14 T1IN T1OUT 9 +V 13 T2IN T2OUT

T CMOS. See Table 5 for more information on possible combinations of interconnections. 14 Ordering Information (continued) PART SYSTEM POWERSUPPLY VOLTAGE (V) 5 Figure 12a. Transmitter Output Voltage vs. Load Current per Transmitter TEMP RANGE PIN-PACKAGE MAX3243ECWI+ 0C to +70C MAX3243ECAI+ 0C to +70C 28 Wide SO 28 SSOP MAX3243ECUI+ 0C to +70C 28 TSSOP MAX3243EEWI+ -40C to +85C 28 Wide SO MAX3243EEAI+ -40C to +85C 28 SSOP MAX3243EEUI+ -40C to +85C 28 TSSOP MAX3243ECTJ+ 0C to +70C 32 TQFN-EP* MAX3243EETJ+ -40C to +85C 32 TQFN-EP* *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. ___________________Chip Information PROCESS: BiCMOS Maxim Integrated MAX3221E/MAX3223E/MAX3243E 15kV ESD-Protected, 1A, 3.0V to 5.5V, 250kbps, RS-232 Transceivers with AutoShutdown +3.3V 26 0.1F 28 C1 0.1F 24 1 C2 0.1F 2 LOGIC INPUTS VCC 27 C1+ V+ C3 0.1F C1C2+ COMPUTER SERIAL PORT 3 MAX3243E V- C4 0.1F C2- 14 T1IN T1OUT 9 +V 13 T2IN T2OUT 10 +V 12 T3IN T3OUT 11 -V 20 R2OUTB 19 R1OUT GND R1IN 4 R2IN 5 Tx 5k 1

T CMOS. See Table 5 for more information on possible combinations of interconnections. 14 Ordering Information (continued) PART SYSTEM POWERSUPPLY VOLTAGE (V) 5 Figure 12a. Transmitter Output Voltage vs. Load Current per Transmitter TEMP RANGE PIN-PACKAGE MAX3243ECWI+ 0C to +70C MAX3243ECAI+ 0C to +70C 28 Wide SO 28 SSOP MAX3243ECUI+ 0C to +70C 28 TSSOP MAX3243EEWI+ -40C to +85C 28 Wide SO MAX3243EEAI+ -40C to +85C 28 SSOP MAX3243EEUI+ -40C to +85C 28 TSSOP MAX3243ECTJ+ 0C to +70C 32 TQFN-EP* MAX3243EETJ+ -40C to +85C 32 TQFN-EP* *Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package. ___________________Chip Information PROCESS: BiCMOS Maxim Integrated MAX3221E/MAX3223E/MAX3243E 15kV ESD-Protected, 1A, 3.0V to 5.5V, 250kbps, RS-232 Transceivers with AutoShutdown +3.3V 26 0.1F 28 C1 0.1F 24 1 C2 0.1F 2 LOGIC INPUTS VCC 27 C1+ V+ C3 0.1F C1C2+ COMPUTER SERIAL PORT 3 MAX3243E V- C4 0.1F C2- 14 T1IN T1OUT 9 +V 13 T2IN T2OUT 10 +V 12 T3IN T3OUT 11 -V 20 R2OUTB 19 R1OUT GND R1IN 4 R2IN 5 Tx 5k 1