TC74AC74FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC74FN Dual D-Type Flip Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC74FN Weight SOL14-P-150-1.27 : 0.12 g (typ.) Features * High speed: fmax = 200 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) *
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 TC74AC374P -- TC74ACT573FW 408 Orderable Part Number TC74AC374P TC74AC377FW TC74AC377FW TC74AC534F TC74AC534FW TC74AC573FT TC74AC573FT-EL TC74AC574FW TC74AC574FW TC74AC574FW-ELP TC74AC574FW-ELP TC74AC574P TC74AC74FN TC74AC74FN TC74AC74FN-ELP TC74AC74FN-ELP TC74AC74FN-ELP TC74AC74P TC74AC86FN TC74AC86FN-ELP TC74AC86P TC74ACT112FN TC74ACT112FN-ELP TC74ACT14FN TC74ACT14FN TC74ACT14FN TC74ACT14FS TC74ACT14FT TC74ACT14FT TC74ACT14FT TC74ACT157FN TC74ACT157P TC74ACT161P TC74ACT174FN TC74ACT174FN-ELP TC74ACT175FN TC74ACT175FN-ELP TC74ACT240FS TC74ACT240FW-ELP TC74ACT240P TC74ACT244FS TC74ACT244FW TC74ACT244FW TC74ACT244FW-ELP TC74ACT257FN-ELP TC74ACT273FW TC74ACT273FW-ELP TC74ACT373F TC74ACT373FS TC74ACT373FT TC74ACT373FT TC74ACT373FW TC74ACT373P TC74ACT374FW TC74ACT374FW TC74ACT374FW TC74ACT374FW TC74ACT374FW-ELP TC74ACT374FW-ELP TC74ACT374FW-ELP TC74ACT374FW-ELP TC74ACT374P TC74ACT541FS TC74ACT573FW
. . . . . . . . . . . . . . . . . 14-SOIC TC74AC32FN-ND Quad 2-Input OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-SOIC TC74AC32FNTR-ND Quad 2-Input OR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-SOIC TC74AC74FN-ND Dual D Flip-Flop with Preset and Clear . . . . . . . . . . . . . 14-SOIC TC74AC74FNTR-ND Dual D Flip-Flop with Preset and Clear . . . . . . . . . . . . . 14-SOIC TC74AC74P-ND Dual D Flip-Flop with Preset and Clear . . . . . . . . . . . . . . . . . 14-Dip TC74AC86FN-ND Quad EXCLUSIVE OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-SOIC TC74AC125FN-ND Quad Bus Buffer (Tri-State). . . . . . . . . . . . . . . . . . . . . . . . . . 14-SOIC TC74AC125FNTR-ND Quad Bus Buffer (Tri-State). . . . . . . . . . . . . . . . . . . . . . . . . . 14-SOIC TC74AC138FN-ND 3 to 8 Line Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-SOIC TC74AC138FNTR-ND 3 to 8 Line Decoder . . . . . . . . . .
TC74AC74FN,TC74AC74FT Dual D-Type Flip Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC74P TC74AC74F Features * High speed: fmax = 200 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) * Symmetrical output impedance: |IOH| = IOL = 24 mA (min) * Capability of driving 50 transmission lines. tpHL Balance
TC74AC74FN,TC74AC74FT Dual D-Type Flip Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC74P TC74AC74F Features * High speed: fmax = 200 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) * Symmetrical output impedance: |IOH| = IOL = 24 mA (min) * Capability of driving 50 transmission lines. tpHL Balance
TC74AC74FN,TC74AC74FT Dual D-Type Flip Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC74P TC74AC74F Features * High speed: fmax = 200 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) * Symmetrical output impedance: |IOH| = IOL = 24 mA (min) * Capability of driving 50 transmission lines. tpHL Balance
TC74AC74FN,TC74AC74FT Dual D-Type Flip Flop with Preset and Clear Note: xxxFN (JEDEC SOP) is not available in Japan. The TC74AC74 is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an "L" level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74AC74P TC74AC74F Features * High speed: fmax = 200 MHz (typ.) at VCC = 5 V * Low power dissipation: ICC = 4 A (max) at Ta = 25C * High noise immunity: VNIH = VNIL = 28% VCC (min) * Symmetrical output impedance: |IOH| = IOL = 24 mA (min) * Capability of driving 50 transmission lines. Balanced pro
TC74AC74FN, TC74AC74FT (Note) The JEDEC SOP (FN) is not available in DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR Japan. The TC74AC74 is an advanced high speed CMOS D- FLIP FLOP fabricated with silicon gate and double - layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. P (DIP14-P-300-2.54) FN (SOL14-P-150-1.27) The signal level applied to the D INPUT is transferred to Q Weight: 0.969 (Typ.)_ Weight: 0.129 (Typ.) OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input to an L level. 1 1 All inputs are equipped with protection circuits against static F (SOP14-P-300-1.27) FT (TSSOP14-P-0044-0.65) discharge or transient excess voltage. Weight : 0.18g (Typ.) Weight : 0.06g (Typ.) PIN ASSIGNMENT FEATURES : High Speedssssesceescccsssesssecseesses fray = 200MHZ (typ. _ e High Spee MAX (typ.) aR 1
TC4S584F TC4S66F TC4S69F TC4S71F TC4S81F TC4SU11F TC4SU69F TC74AC00FN TC74AC00FT TC74AC02FN TC74AC02FT TC74AC04FN TC74AC04FT TC74AC04P TC74AC05FN TC74AC08FN TC74AC08FT TC74AC10FN TC74AC11FN TC74AC14FN TC74AC14FT TC74AC20FN TC74AC32FN TC74AC32FT TC74AC32P TC74AC74FN TC74AC74FT TC74AC74P TC74AC86FN TC74AC86FT TC74AC112FN TC74AC125FN TC74AC125FT TC74AC126FN TC74AC138FN TC74AC138FT TC74AC139FN TC74AC139FT TC74AC151FN TC74AC153FN TC74AC157FN TC74AC157FT TC74AC161FN TC74AC161FT TC74AC163FN TC74AC163FT TC74AC164FN TC74AC164FT TC74AC164P TC74AC166FN TC74AC174FN TC74AC174FT TC74AC175FN TC74AC175FT TC74AC240FT TC74AC244FT TC74AC245FT TC74AC257FN TC74AC258FN TC74AC273FT TC74AC280FN TC74AC283FN TC74AC367FN TC74AC367FT TC74AC373FT TC74AC374FT Page 14 14 14 14 14 14 14 14 14 14 14 19 19 19 19 19 19 19 19 19 19 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 Device TC74AC390FN TC74AC
TC74AC74FN, TC74AC74FT (Note} The JEDEC SOP (FN) is not available in DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR Japan. The TC74AC74 is an advanced high speed CMOS D - FLIP FLOP fabricated with silicon gate and double - layer metal wiring C2MOS technology. Ii achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to Q QUTPUT during the positive going transition of the CK pulse. P (DIP14-P-300-2.54) FN (SQOL14-P-150-1.27) Weight : 0.969 (Typ.) Weight: 0.129 (Typ.) CLR and PR are independent of the CK and are Xe eee accomplished by setting the appropriate input to an L level. 1 1 All inputs are equipped with protection circuits against static F(SOP14-P-300-1.27) FT {TSSOP14-P-0044-0.65) discharge or transient excess voltage. Weight : 0.18g(Typ.) Weight : 0.06g (Typ.) PIN ASSIGNMENT FEATURES : High Speedsessssscsssseseccssssssseseasenees faa = 200MHZ (typ. e High Spee MAX (t